1) Field of the Invention
The present invention relates to a technology for transmitting and receiving a plurality of bits in parallel in synchronization with clocks, which improves an error correction capability in data transmission without increasing the number of signal lines and without causing a transmission delay for a reliable data transmission.
2) Description of the Related Art
When N-bit data is transmitted by using a bus between large-scale-integrated (LSI) devices, such as a central processing unit (CPU) and a crossover LSI or between modules in an LSI device, the data is divided into N/m bits at m clocks. For example, when 128-bit data is transmitted by using a 32-bit bus, the 128-bit data are divided into 32 bits, and the 32-bit data are transmitted at four clocks.
In the conventional data transmission between the LSI devices or between the modules, a parity bit is used to cope with a transmission error. FIG. 15 is a schematic for explaining a conventional error correction method in inter-module data transmission.
In the example shown in FIG. 15, 128-bit data is divided into 32 bits and transmitted at four clocks. One parity bit is added to one 32-bit clock data in a bit direction to transmit 33-bit data. A parity bit is added to each bit position of the 32 bits in a clock direction. The data is transmitted in the next additional cycle of the 4-clock data cycle.
In the vertical/horizontal parity coding scheme, one bit error in N-bits can be corrected, and a 2-bit error can be detected. For example, in the example shown in FIG. 15, when an error “X” occurs at a bit position “32” of data transmitted at the first clock, the error can be corrected by using the parity bit added to the data and the parity bit added to the bit position “32” in a clock direction (see, for example, Japanese Patent Laying-Open No. 6-125331 and Mitani Masaaki, “Yarinaoshi no tame no kougyou sugaku”, p. 48, CQ Publishing Co., Ltd., Jan. 1, 2001).
However, in the conventional vertical/horizontal parity coding scheme, it impossible to correct an error having equal to or more than two bits. In addition, when an even number of errors occur at data at the same clock or the same bit position, it is impossible to detect the error.